A Study of Power Consumption Using High-Speed and Low-Power Comparator advanced ADC

Today, the high performance of electronic equipment is dependent on the development of high-speed analog to digital converter (ADC). And, the most common structure of high-speed ADC is Flash ADC. The design of comparator is the most critical part in the Flash ADC, since the speed and the resolution of Flash ADC is determined by the comparator. In this paper, a high-speed low-power comparator, which is used in a 2 Gsps, 8 bit Flash ADC, is designed and simulated. Based on 0.18 um TSMC CMOS process model, the comparator circuit is simulated with a 1.8V power supply in Cadence environment. The result shows that it can work at a 2GHZ clock frequency, and the dynamic power consumption is only 1.2mW, with 123.5ps transmission delay. In addition, the average offset voltage of this comparator is only 676.3uV, which can meet the requirements of an 8-bit Flash ADC.There have three types of comparator can provide the high speed, such as multistage open loop comparator, the dynamic latch comparator, and the preamplifier-latch comparator. The multistageopen loop comparator can meet high-speed and high-precision, but it is hardly can provide the speed more than 1Gsps.The dynamic latch comparator is widely utilized to satisfy the need for high-speed. However, this kind of comparator has large offset voltage which affects the resolution of Flash ADC. The preamplifier-latch comparator can obtain high-speed and high-resolution because of its circuit structure. In this paper, by considering factors of speed and resolution, preamplifier-latch comparator is the choice for Flash ADC.