Design Optimization and Fault Tolerance in Network on Chips (NOC)

NoC is a rising worldview for on chip data transfer of vast VLSI systems actualized on a single chip. In a NoC system, modules, for example, processor centers, memory centers and specialized intellectual property (IP) squares trade data utilizing an on-chip network. NoC replaces committed, design-explicit interconnection (transports, point-to-point ports, and so on.) in SoC with adaptable, universally useful network, and it sets up a correspondence between modules Under the imperative of deadlock opportunity, we make utilization of the intrinsic repetition in NoCs because of numerous ways between parcel sources and sinks and propose distinctive fault-tolerant routing schemes to accomplish much preferred fault tolerance abilities over conceivable with traditional routing schemes. The main aim of this paper is to describe the concept of Network on chips (NOC), its design space and automation tools, architecture of Noc and Design, Optimization of Networks-On-Chip, algorithms and fault tolerance in NoC.